Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!zaphod.mps.ohio-state.edu!sol.ctr.columbia.edu!ira.uka.de!smurf!gopnbg!mcshh!apal!root From: root@apal.mcshh.UUCP (Andreas Mueller) Newsgroups: comp.sys.amiga.hardware Subject: How do they run async clocks Message-ID: Date: 18 Nov 90 16:14:12 GMT Distribution: comp Lines: 17 -- Does anybody know, how the asyncronus clocking (on 68k20/30/.. boards) is handled? I mean, how do they syncronize the fast clock with the slow 7.1.. MHz clock. I think, syncronizing is only done when the CPU accesses 32 bit ram -> chip ram | chip ram -> 32 bit ram. But this would cause some waits (except the 7.1.. MHz clock is a divider of the CPU clock). Any comments ..... ?:) ----------------------------------------------------------------------------- /***************************************************************************** * Andreas Mueller (A1020) | "Who left a footprint in my chase?" * * UUCP: root@apal.mcshh.UUCP | "Strong typing is for weak minds!" (unknown?) * *****************************************************************************/