Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!newstop!exodus!exodus-bb!khb From: khb@loglady.Eng.Sun.COM (Keith Bierman fpgoup) Newsgroups: comp.sys.next Subject: Re: Next, 40, Sparc, 2 Message-ID: Date: 20 Nov 90 02:16:49 GMT References: <1990Nov12.135515@Atherton.COM> <11090@pt.cs.cmu.edu> <30017@boulder.Colorado.EDU> <1990Nov19.173120.1@lucy.claremont.edu> Sender: news@exodus.Eng.Sun.COM Organization: Sun MegaSystems Lines: 124 In-reply-to: jack@lucy.claremont.edu's message of 20 Nov 90 01:31:20 GMT In article <1990Nov19.173120.1@lucy.claremont.edu> jack@lucy.claremont.edu writes: ... > I don't wish to start a flame war (although its a little late for that) but I want to point out that NeXT users are not alone in thinking that the SPARCStation 2 is not a particularly good computer for the money. The quotes that follow are from UNIX Today!, November 12, 1990, page 88: It appears that Sun is able to come close to the integer performance of our RS/6000, but to do so, they require a 40-MHZ clock rate, versus the 20 MHz on our POWERStation 320 ---Judy Radlinsky, IBM They're running that thing at 40 MHz generating 28 MIPS. That's anemic. That's bad. That's terrible. ---Paul Bemis, program manager, HP/Apollo Ah, unbiased marketing folks. Misc answers, not all equally good. Use with care, salt etc.. 1) A claimed SPARC advantage was easy scaling .... so why is hitting fast clocks suddenly bad ???? ;> 2) there are several ways to make machines go fast, varying from strange ISA's, fast clocks, clever implementations (multiple instructions per clock, superscalar, etc.) and various interactions with the software (mostly the compiler and libraries). The Multiflow machines ran up to 50mflops (sustained) with an 8mhz clock. Had they stuck around, 16mhz and 20mhz were plausible.... with their machine 40mhz would have been a while in coming (guessing ;>). Should one have predicted that the 386 would blow the MF away on applications due to its higher clock ? Should one have predicted that the MF would quickly get high clock rates ? Neither prediction would have been very reasonable. When evaluting a system, any sensible purchaser will test something they care about on the various machines. How the machines go fast is mostly (entirely ?) the vendors buisness. There are obvious exceptions.... week long compiles are user visible ;> SPARC vendors, in the last rounds chose to go for quick clocks. Within limits this can be the "easy" road. At HotChips SPEC (the company, not the benchmarking group) gave some data about their 200+mhz SPARC chipset. Past 2ns clocks (400mhz) things get very hard ;> Other vendors have done other things. Again, from HotChips the LSI/Hyundai/Metaflow project, which is a superscalar machine with out of order execution. This is very nifty technology, partly made possible by virtue of not having an overly polluted instruction set. At 40mhz they claimed at LEAST triple the performance of the sparcstation 2, a 40mhz box. Perhaps significantly better. Sun has not announced any plans wrt to this chip (nor the 200+mhz SPEC set) but one would think that Sun won't insist on using anything worse (at similar price points, etc.) Matsushita, via Solbourne, has done a chip (shipping in their new desktops) with wide data paths and multiple stuff on a chip (I forget the details; but higher integration is often a way to get higher performance). Solarix (I think) has announced what they call the "a module" which is a chipset+cache on a carrier which plugs into a board.... thereby making upgrades in place plausible (ala the HP 030 to 040; which has had to tide HP users ... since there have not been 040's which meet HP's quality standards). I would not venture to guess which of the paths Sun is chosing.... but there will be lots of SPARC stuff to chose from. Many of the tricks in the IBM box apply quite handily to other ISA's.... (e.g. register renaming, etc.); admittedly there are things which aren't "portable". 3) Exercise for the student. Locate a 4/60, a 4/65, a 4/75, and an IBM 320. Pop the tops of the SPARCs off. Compare the complexity . Now pop the top off the IBM. Looks rather apallingly complicated. One might venture to guess that building their 20mhz box was harder (more parts+more steps usually implies greater cost, all other things being equal) than building the SPARC 40mhz box. All in all, it's our job (as designers) to build SYSTEMS (hw+sw) which perform well on real problems. It's the job of salescritters and marketeers to edcuate folks what to look at. Mhz, MIPS and LINPACK flops aren't it .... we will all suffer for a long time for not having moved the discussion to more sensible things ages ago (e.g. lfk's, specmarks, etc.). .... They're basically coming up to parity with the DECStation 5000 now. And we're in the middle of our next generation of product development. ---Charlie Giorgetti, marketing manager, DEC And how many DS5000 have shipped ? It is easy to announce machines, it is harder to build and ship them. I'd guess that by March (if not sooner) the number of 40mhz SPARC boxes will be at least 2x the number of 33mhz DS5000's. Also, one wonders how much Charlie knows about Sun project plans ;> It seems to be that he is implying that such programs are serial, rather than parallel or pipelined. DEC doesn't operate serially, why should anyone else ? Don't get me wrong. The NeXT is a fun box (more for the sw than for any cleverness in the hw). I wish you all well. I do hope, for my sanity if nothing else, that you find something more reasonable than mhz rates, 10 line benchmarks, etc. to discuss. If you must chat about benchmarking, there is comp.benchmarks which is dedicated to this sort of thing; and the level of discourse has been mercifully higher. Cheers. -- ---------------------------------------------------------------- Keith H. Bierman kbierman@Eng.Sun.COM | khb@chiba.Eng.Sun.COM SMI 2550 Garcia 12-33 | (415 336 2648) Mountain View, CA 94043