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From: dkoski@hercules.as.arizona.edu (David Koski)
Newsgroups: comp.sys.next
Subject: Re: Next, 40, Sparc, 2
Message-ID: <494@organpipe.UUCP>
Date: 20 Nov 90 16:48:59 GMT
References: <SMITHW.90Nov13181532@hamblin.hamblin.math.byu.edu> <30017@boulder.Colorado.EDU> <1990Nov19.173120.1@lucy.claremont.edu>
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In article <1990Nov19.173120.1@lucy.claremont.edu> jack@lucy.claremont.edu writes:
>At 40 MHz the SPARC Chip appears to close to the edge of its performance.  How
>much faster can you push the clock speed?  60 MHz?  80 MHz?  Another problem is
>when you begin to up the clock speeds you naturally raise the cost of the other
>components and wind up with a more expensive system.  Sun may be making a

Well, not really.  An asychronous bus will allow slower parts to be used with
faster parts.

David Koski