Path: utzoo!utgpu!news-server.csri.toronto.edu!helios.physics.utoronto.ca!physics.utoronto.ca!chlebana
Newsgroups: comp.sys.sgi
From: chlebana@physics.utoronto.ca (Frank Chlebana)
Subject: 4D35 VME questions.
Message-ID: <1990Nov21.135845.11240@helios.physics.utoronto.ca>
Organization: University of Toronto Physics/Astronomy/CITA
Date: 21 Nov 90 18:58:46 GMT

The glossy spec sheet for the 4D/35 says that block mode transfers are
supported on the VME interface. We are currently using the 4D/25S to 
read data from an external VME crate into the SGI. The SGI uses 
programmed IO to transfer data from the interface board to memory.
That is, cpu registers are loaded with the data from the VME address,
then stored into the user virtual address. During the transfer the
cpu is unavailable for computation. Ideally what I would like is to 
have a DMA controller handling the transfer. 

Does the 4D/35 actually use block transfers when it is the VME master?
How do you specify that you want to use block transfers, a different
address range, load a register or what?

Do I still have to use PIO on the 4D/35 or does it have DMA capability
when it acts as the VME master? Is the cpu free to do work while the
transfer is in progress (SGI is the VME master).

I would like some more technical info regarding accessing the VME adaptor.
Since the 4D/35 is "build to support release 3.3" of system software I
believe that the device driver will work on the 4D/35, however I want
to be able to take advantage of any new bells and whistles.

Are there any hardware manuals available?

I noticed that the VME interface no longer sits on the system bus. Does
this allow system bus cycles to occur while VME transfers occur? Will
I be able to receive ethernet messages, access the SCSI disk etc WHILE
a VME transfer is in progress?

Please send helpful information to 

chlebana@oldkat.physics.utoronto.ca

Thanks.

Frank Chlebana
University of Toronto
Dept. of Physics
60 St. George Street
Toronto, Ontario. CANADA
M5S 1A7