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From: lbr@holos0.uucp (Len Reed)
Newsgroups: comp.unix.programmer
Subject: Re: Makefiles -- .c and .h
Message-ID: <1990Nov16.164614.23206@holos0.uucp>
Date: 16 Nov 90 16:46:14 GMT
References: <9011151442.AA02010@decpa.pa.dec.com>
Organization: Holos Software, Inc., Atlanta, GA
Lines: 39
Eepeep: WHAT, Noname?

In article <9011151442.AA02010@decpa.pa.dec.com> ellis@ultra.dec.com (David Ellis 15-Nov-1990 0915) writes:
=Consider a Makefile for an executable built from a large number of .o files, 
=each separately compiled from a .c file.
=
=If we use a single .c.o rule for compiling all the source files, then it 
=seems that a change in a .h file that is #include'd in a .c file will
=not be picked up by Make to automatically force recompilation of the .c file.
=
=One workaround is to replace the single .c.o rule with a collection of rules, 
=one for each .o file, listing the dependencies on the .h files #include'd in
=the corresponding .c file.  But this is a lot of writing, and if we change
=the "#include" lines in any .c file, we have to update the Makefile with the
=corresponding change.
=
=Is there a simpler way?

You don't want a separate rule for each C file, just a separate dependency
line.  Like this:

MOST = this.h that.h more.h another.h etc.h
one.o : $(MOST) header_a.h header_b.h
two.o : $(MOST) header_c.h
three.o : $(MOST)

.c.o :
	$(CC) $(CFLAGS) $<

The MOST macro is used to group headers that most C files include.  You only
have one rule.  Note that x.o depends implicitly upon x.c for all x.  In
this example the rule is superfluous, since it's just the default.

Now, what about those dependency lines?  There are dependency
checkers out there, and for complicated projects using one is far better
than trying to maintain these by hand.
-- 
Len Reed
Holos Software, Inc.
Voice: (404) 496-1358
UUCP: ...!gatech!holos0!lbr