Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!romp!auschs!awdprime!doorstop.austin.ibm.com!tif
From: tif@doorstop.austin.ibm.com (Paul Chamberlain)
Newsgroups: comp.unix.programmer
Subject: Re: Makefiles -- .c and .h
Message-ID: <4307@awdprime.UUCP>
Date: 21 Nov 90 17:19:08 GMT
References: <9011151442.AA02010@decpa.pa.dec.com>
Sender: news@awdprime.UUCP
Reply-To: tif@doorstop.austin.ibm.com (Paul Chamberlain)
Organization: IBM AWD, Austin, TX
Lines: 18
Summary:
Expires:
Sender:
Followup-To:
Keywords:

In article <9011151442.AA02010@decpa.pa.dec.com> ellis@ultra.dec.com (David Ellis 15-Nov-1990 0915) writes:
>a change in a .h file that is #include'd in a .c file will not be picked
>up by Make to automatically force recompilation of the .c file.
>
>One workaround is to [use] a collection of rules, ...

It has already been pointed out that if one .c file does an include you
can simply add this to the bottom of the makefile with no other changes:

	file1.o: include1.h

But I thought it would be useful to point out these syntaxes as well:

	file1.o file2.o: common.h
	$(ALL_OBJS): common1.h common2.h

Paul Chamberlain | I do NOT represent IBM.     tif@doorstop, sc30661 at ausvm6
512/838-7008     | ...!cs.utexas.edu!ibmchs!auschs!doorstop.austin.ibm.com!tif