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From: sralston@srwic.UUCP (Steve Ralston)
Newsgroups: comp.unix.programmer
Subject: Re: Makefiles -- .c and .h
Message-ID: <195@srwic.UUCP>
Date: 20 Nov 90 07:50:51 GMT
References: <9011151442.AA02010@decpa.pa.dec.com> <1990Nov15.172323.23431@athena.mit.edu> <6268@minyos.xx.rmit.oz.au> <1990Nov18.204155.6925@athena.mit.edu>
Organization: Steve Ralston   Wichita, KS
Lines: 32

Of the many replies to this subject, I have not seen mention of the method
which I am currently using, namely:

	gcc -M file.c

For those without gcc, press the 'n' key:
According to the man page on gcc:

	  -M   Tell the	preprocessor to	output a rule suitable for
	       make(1) describing the dependencies of each source
	       file.  For each source file, the	preprocessor outputs
	       one make-rule whose target is the object	file name for
	       that source file	and whose dependencies are all the
	       files #included in it.  This rule may be	a single line
	       or may be continued with	\-newline if it	is long.

	       -M implies -E.

	  -E   Run only	the C preprocessor.  Preprocess	all the	C
	       source files specified and output the results to
	       standard	output.

It's not real difficult to incorporate this command right in your Makefile
(piping to sed, etc, or whatever) so that when you type something like:

	make depend

the dependency lists are recreated from scratch.
-- 
Steve Ralston						sralston@srwic.UUCP
235 N Zelta						voice: 316-686-2019
Wichita, KS 67206			..!uunet!ncrlnk!ncrwic!srwic!sralston