Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!yale!think.com!mintaka!bloom-beacon!eru!hagbard!sunic!isgate!krafla!adamd From: adamd@rhi.hi.is (Adam David) Newsgroups: sci.electronics Subject: RAM access times Message-ID: <2416@krafla.rhi.hi.is> Date: 18 Nov 90 02:52:33 GMT Organization: University of Iceland Lines: 13 I am interested in how RAM access times are specified. Say a 150ns RAM chip is read and immediately written again without changing the address or deselecting the chip between. What is the total time taken? The read cycle must take 150ns, but when the write cycle begins the correct memory cell is already addressed. How long does it take to actually write to (or read from) a memory cell without considering addressing delays? Does anyone have experience or other inside knowledge about this issue? Would there be any difference between the times for SRAM or DRAM? Thanks ahead for any help, Adam David. adamd@rhi.hi.is