Newsgroups: sci.electronics
Path: utzoo!henry
From: henry@zoo.toronto.edu (Henry Spencer)
Subject: Re: RAM access times
Message-ID: <1990Nov18.225425.22234@zoo.toronto.edu>
Organization: U of Toronto Zoology
References: <2416@krafla.rhi.hi.is>
Date: Sun, 18 Nov 90 22:54:25 GMT

In article <2416@krafla.rhi.hi.is> adamd@rhi.hi.is (Adam David) writes:
>I am interested in how RAM access times are specified. Say a 150ns RAM chip is
>read and immediately written again without changing the address or deselecting
>the chip between. What is the total time taken? The read cycle must take 150ns,
>but when the write cycle begins the correct memory cell is already addressed.
>How long does it take to actually write to (or read from) a memory cell without
>considering addressing delays?

It depends on the chip, is the fast answer.  Assuming you are talking about
reading and then writing the *same* location -- you don't make that clear --
then there can sometimes be a speed improvement.  A lot depends on the
details of the memory technology you are using.

You're also overlooking another complication:  the speed quoted for a chip
is usually the read access time.  That is *not* necessarily the full time
needed for a read cycle.  DRAMs, in particular, need recovery time after
the read, and thus have a cycle time substantially longer than their access
time.  On the other hand, they can also do read-modify-write cycles that
take less time than independent reads and writes.  A DRAM data sheet will
often spend five pages on functional description and electrical parameters,
followed by ten pages of timing diagrams and tables of timing limits.  A
precise answer would require a far more detailed question.
-- 
"I don't *want* to be normal!"         | Henry Spencer at U of Toronto Zoology
"Not to worry."                        |  henry@zoo.toronto.edu   utzoo!henry