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From: ftpam1@acad3.fai.alaska.edu (MUNTS PHILLIP A)
Newsgroups: sci.electronics
Subject: Re: RAM access times
Message-ID: <1990Nov20.185609.7598@hayes.ims.alaska.edu>
Date: 20 Nov 90 18:56:09 GMT
References: <2416@krafla.rhi.hi.is> <1990Nov18.225425.22234@zoo.toronto.edu> <2425@krafla.rhi.hi.is>
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In article <2425@krafla.rhi.hi.is>, adamd@rhi.hi.is (Adam David) writes...
>Yes, I definitely meant reading the memory contents before writing new data at
>the same location. I was interested in the comparison between various types of
>memory but am specifically interested in the newer pseudo-static DRAMs (with
>on-chip refresh circuitry for times of little activity). I have no access to the
>data sheets for any of these at present.
> 
>Let me guess... , pseudo-static DRAMs are still DRAMs although they have an
>8-bit data path and non-multiplexed address lines. Therefore they have similar
>characteristics internally and would take a while longer to complete a full
>access cycle at any particular address than the quoted access times. With 150ns
>RAM a single read cycle followed by a single write cycle would take 150ns plus
>some recovery time, twice over. A combined read-write cycle would take twice
>150ns plus the recovery time once. If this is true the write part of the cycle
>may not begin until the first 150ns are over, to allow the data to be read.
>Is this in fact the case? Does this then mean that no greater speed is possible
>for data exchange operations without moving to faster components?
> 
>For completeness, here is the order of signals (still guessing):
> 
>                  ._______________________________________________.
>Address lines. ___|  stable address of valid memory location      |_____
>                  |_______________________________________________|
> 
>       _______________.                                       ._________
>/CE.                  |_______________________________________|
> 
>       _________________.               ._______________________________
>/OE.                    |_______________|
>                                        
>       ___________________________________.               ._____________
>/WE.                                      |_______________|
> 
>                                      .__.._________________.
>Data lines. __________________________|rd||stable write data|___________
>                                      |__||_________________|
> 
> 
>each horizontal bar represents 10 ns.
> 
>Is this the best performance we can expect from the memory chip?
>Or must it be even worse for any/all single-ported devices?
> 
>Thanks for any replies.
> 
>Adam David.     adamd@rhi.hi.is

     Just happen to have a new data sheet from Motorola, for the MCM518128,
a 128K x 8 PSRAM.  Parameters for 80 and 100 ns parts are listed, but I will
consider here only the 100 ns device.

     The random read or write cycle time is 160 ns minimum.  The chip select
access time is 100 ns.  The precharge time (chip select inactive) is 50 ns.
I presume the missing 10 ns is lost in transition times.

     The read-modify-write, which follows your diagram nicely (good guessing!)
has a minimum cycle time of 235 ns.  Note that the output drivers require as
much as 30 ns to turn off.  (In other words, wait 30 ns after deactivating the
read pulse before driving write data onto the bus.)

     I have data sheets for one or two other PSRAM's but I suspect they are
pretty much the same.  I was originally interested in them because the address
is latched on the falling edge of chip select, allowing the address latches to
be eliminated on a multiplexed address/data bus.

Philip Munts N7AHL
NRA Extremist, etc.
University of Alaska, Fairbanks