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From: mshute@cs.man.ac.uk (Malcolm Shute)
Newsgroups: comp.arch
Subject: Re: registerless architecture
Message-ID: <1941@m1.cs.man.ac.uk>
Date: 26 Nov 90 13:20:54 GMT
References: <1990Nov12.145410.29035@cs.cmu.edu> <3168@ns-mx.uiowa.edu>
Sender: news@cs.man.ac.uk
Reply-To: mshute@cs.man.ac.uk (Malcolm Shute)
Organization: Department of Computer Science, University of Manchester UK
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In article <3168@ns-mx.uiowa.edu> jones@pyrite.cs.uiowa.edu (Douglas W. Jones,201H MLH,3193350740,3193382879) writes:
>My Ultimate RISK (Computer Architecture News, 1988) is a memory-to-memory
>architecture with no registers in the instruction execution unit other
>than the PC.  It has no arithmetic unit in the IEU either, which is why
>I call it an IEU instead of a CPU.  The registers and arithmetic unit(s)
>are out on the memory bus.  It was proposed as a purely pedagogical
>exercise, [...]

Mine went the other way (Microelectronics Journal Vol 15, No 3&5)...
It had an ACC, but no PC.

Instead there was an instruction in location zero of memory which,
when executed, had its address field incremented, written back,
and used as the address of the next instruction to be fetched.

You might have gathered, that it wasn't tuned for high speed use!
Instead, the aim was to see if I could design a 16-bit processor
using only 600 transistors.  There were only 4 instructions in the
instruction set, and getting it to do the equivalent of a PDP11
MOV memory, memory  operation took about 7 instructions, in much
the same contorted sort of a way as Single Instruction Computers.

It was a fun exercise.  Probably not much use though.
--

Malcolm SHUTE.         (The AM Mollusc:   v_@_ )        Disclaimer: all