Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!wuarchive!psuvax1!psuvm!dxb132
From: DXB132@psuvm.psu.edu
Newsgroups: comp.arch
Subject: Re: Real Time/Cache
Message-ID: <90332.233001DXB132@psuvm.psu.edu>
Date: 29 Nov 90 04:30:01 GMT
References: <11190@pt.cs.cmu.edu> <90331.001007DXB132@psuvm.psu.edu>
 <11228@pt.cs.cmu.edu>
Organization: Penn State University
Lines: 13

In article <11228@pt.cs.cmu.edu>, lindsay@gandalf.cs.cmu.edu (Donald Lindsay)
says:

>trend to on-chip cache, and external SRAM is surely going to be
>slower than that. (Aside from an extra clock or two of access, there
>is often a bus width difference.) So, although uncached references

Any Transputer fans out there? I seem to recall (not really sure) that
the Transputer had 2K or 4K of static RAM on-chip, that was up to software
to use (i.e. it wasn't a cache in the usual sense).
Your point is well taken, however.

-- Dan Babcock