Path: utzoo!utgpu!watserv1!watmath!att!att!linac!uwm.edu!ogicse!intelhf!ivan!kumarr
From: kumarr@ivan.hf.intel.com (Kumar Ranganathan)
Newsgroups: comp.arch
Subject: page fault handling on the 80386
Keywords: ss,esp
Message-ID: <1990Nov28.214348.21444@ivan.hf.intel.com>
Date: 28 Nov 90 21:43:48 GMT
Organization: Industrial Computing Division - Intel Corp. - Hillsboro Or.
Lines: 14

On the 386, a MOV into the SS register causes the next instruction to
execute with interrupts disabled. This is to enable ESP to be loaded
following the move into SS, so that the stack is consistent before interrupts
come in(the LSS instruction does the same thing). Consider the following 
instruction sequence:

MOV SS, stack_seg
MOV ESP, stack_ptr

Assume paging is enabled and the variables stack_seg and stack_ptr are
in different pages. If the reference to stack_ptr generates a page fault,
the page fault handler will not be able to get control since interrupts
will be disabled. 
What state will the processor be in under these circumstances ?