Path: utzoo!utgpu!watserv1!watmath!att!linac!pacific.mps.ohio-state.edu!zaphod.mps.ohio-state.edu!wuarchive!hsdndev!spdcc!iecc!Postmaster
From: johnl@iecc.cambridge.ma.us (John R. Levine)
Newsgroups: comp.arch
Subject: Re: page fault handling on the 80386
Message-ID: <9011290934.AA20848@iecc.cambridge.ma.us>
Date: 29 Nov 90 14:34:56 GMT
Sender: Postmaster@iecc.cambridge.ma.us
Organization: I.E.C.C.
Lines: 23
In-Reply-To: <1990Nov28.214348.21444@ivan.hf.intel.com>

In article <1990Nov28.214348.21444@ivan.hf.intel.com> you write:
>On the 386, a MOV into the SS register causes the next instruction to
>execute with interrupts disabled. ...
>[if you load SS and then SP, and the load of SP causes a page fault,
>what happens?]

Consult the Intel 80386 Programmer's Reference Manual, order number 230985,
available from Intel for about $25, probably even less if you work for them.

Section 9.8.14.2 addresses this very situation.  In general, traps and
exceptions switch to a different privilege level or even a different task.
Each privilege level in a task has a different stack, so it is no problem
that the faulting code has a bogus stack -- nothing is pushed on it.  It
mentions that if the operating system for some reason takes page faults in
the faulting tasks's context, then code in that task should only use the
indivisible LSS instruction rather than two moves.

See section 6.3.4.1 for an overview of task switching.  The 486 Programmer's
Reference Manual, order number 240486, contains the same information in
sections 9.9.14.2 and 6.5.1. 

Regards,
John Levine, johnl@iecc.cambridge.ma.us, {spdcc|ima|world}!iecc!johnl