Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!wuarchive!emory!hubcap!Jingwen
From: wangjw@usceast.cs.scarolina.edu (Jingwen Wang)
Newsgroups: comp.parallel
Subject: Re: Shared Memory over a Bus?
Message-ID: <11911@hubcap.clemson.edu>
Date: 28 Nov 90 14:25:27 GMT
Sender: fpst@hubcap.clemson.edu
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Approved: parallel@hubcap.clemson.edu

Dear Mr. Folta,
   Your intuition is correct. In fact we had built a 8-processor multiprocessor
with a similar architecture in China using the TMS 320C25. The Broadcast bus
is a 16-bit parallel bus link all processors' communication memoreis. The
difference is that in our system each processor can broadcasts messages to
all the others. It is thus designed to meet the communication requirements
of continuous system simulation applications. Each processor uses a dual-
port memory as the communication memory attached to the bus.
   We have made simulations for this system and the results indicated
very attractive performance over a shared global memory architecture.
The system has a PC-AT computer as the front end host together with a
graphics terminal for dynamic visual display.
   Although your basic idea is wonderful, there is still problem to meet
the time constraints on your system. A 36Mbytes/sec in-coming data rate
can hardly be manageble by even the fastest processors to-date. You can
not simply execute that many instructions per second. Even if a DMA
mode transmission is used, it is still a headache.
   The design would not be a trifle one since high data rates will incur
lots of reliability problems.
   Only for your reference. Hope it helps a little.

Jingwen Wang

Department of Electrical & Computer Engineering
University of South Carolina
Columbia, SC 29208