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From: andrew@frip.WV.TEK.COM (Andrew Klossner)
Newsgroups: comp.sys.m88k
Subject: Re: Request help with interrupt/exception handling
Message-ID: <9591@orca.wv.tek.com>
Date: 26 Nov 90 15:55:12 GMT
References: <1990Nov21.163055.29746@eagle.lerc.nasa.gov>
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Organization: Tektronix, Wilsonville, Oregon
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|	ldcr	r1,PSR		; prepare to re-enable exceptions
|	and	r1,r1,0XFFF7	; but leave interrupts disabled
|	stcr	r1,EPSR
|
|	or.u	r1,r0,hi16(fpu_snip+2)
|	or	r1,r1,lo16(fpu_snip+2)
|	stcr	r1,SNIP
|
|	or.u	r1,r0,hi16(fpu_sfip+2)
|	or	r1,r1,lo16(fpu_sfip+2)
|	stcr	r1,SFIP
|
|	ld	r1,sp,16
|	rte			; flush pending FPU operations

The RTE instruction will enable the FPU but shadows will still be
frozen, so any FPU exceptions will take the ERROR exception vector.

You could put a fast bypass around this code by checking to see if SSBR
is zero.  If so, no scoreboard registers were set, and so there can't
be any pending FPU exceptions.  (This assumes up-to-date silicon.)

By the way, there's no code here to clean up the data pipeline.  You
have to do that on every interrupt exception.

  -=- Andrew Klossner   (uunet!tektronix!frip.WV.TEK!andrew)    [UUCP]
                        (andrew%frip.wv.tek.com@relay.cs.net)   [ARPA]