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From: gronski@locust.wpd.sgi.com (Jan Gronski)
Newsgroups: comp.sys.sgi
Subject: Re: VeriLog (question)
Message-ID: <1990Nov30.173124.2575@relay.wpd.sgi.com>
Date: 30 Nov 90 17:31:24 GMT
References: <9011281734.AA01033@frodo.Physics.McGill.CA>
Sender: news@relay.wpd.sgi.com ( CNews Account )
Reply-To: gronski@locust.wpd.sgi.com (Jan Gronski)
Organization: Silicon Graphics, Research & Development
Lines: 18
Cc: penguins

In article <9011281734.AA01033@frodo.Physics.McGill.CA>, loki@physics.mcgill.ca (Loki Jorgenson Rm421) writes:
|> 
|> 	Does anyone have any experience with the digital electronics
|> simulation program, VeriLog (on IRIS 4Ds)? It is distributed by
|> Cadence Design Systems.

At SGI there are a few Verilog and Verilog-XL licenses. We have been running
them successfully on 4D240GTXs and see no reason why they should not run a 
4D25s. We are negotiating with Cadence to obtain another licence which we
would like to try out on a 4D25. We have run simulations of at least 2 major 
chips, FDDI MACs from some 3rd party vendors, without any difficulties.

Indeed, Cadence does not have an official SGI port. We have been running
a MIPS version. This required a few small changes in make files. Cadence
is reluctant to recognize this as an official port. They are wary of the
cost of supporting yet another port.

jan