Path: utzoo!utgpu!watserv1!watmath!att!linac!pacific.mps.ohio-state.edu!zaphod.mps.ohio-state.edu!wuarchive!uunet!ncrlnk!ncr-mpd!Mike.McManus From: Mike.McManus@FtCollins.NCR.com (Mike McManus) Newsgroups: sci.electronics Subject: Re: RAM access times Message-ID: Date: 26 Nov 90 13:54:08 GMT References: <2416@krafla.rhi.hi.is> <1990Nov18.225425.22234@zoo.toronto.edu> <2425@krafla.rhi.hi.is> Sender: uucp@ncr-mpd.FtCollins.NCR.COM Organization: NCR Microelectronic Products, Ft. Collins, CO Lines: 69 In-reply-to: adamd@rhi.hi.is's message of 20 Nov 90 01:27:30 GMT In article <2425@krafla.rhi.hi.is> adamd@rhi.hi.is (Adam David) writes: > >>I am interested in how RAM access times are specified. Say a 150ns RAM > >>chip is read and immediately written again without changing the address > >>or deselecting the chip between. What is the total time taken? The read > >>cycle must take 150ns, but when the write cycle begins the correct memory > >>cell is already addressed. How long does it take to actually write to > >>(or read from) a memory cell without considering addressing delays? > > Yes, I definitely meant reading the memory contents before writing new data > at the same location. I was interested in the comparison between various > types of memory but am specifically interested in the newer pseudo-static > DRAMs (with on-chip refresh circuitry for times of little activity). I have > no access to the data sheets for any of these at present. > > >You're also overlooking another complication: the speed quoted for a chip > >is usually the read access time. That is *not* necessarily the full time > >needed for a read cycle. DRAMs, in particular, need recovery time after > >the read, and thus have a cycle time substantially longer than their access > >time. On the other hand, they can also do read-modify-write cycles that > >take less time than independent reads and writes. ... > With 150ns RAM a single read cycle > followed by a single write cycle would take 150ns plus some recovery > time, twice over. A combined read-write cycle would take twice 150ns plus > the recovery time once. If this is true the write part of the cycle may > not begin until the first 150ns are over, to allow the data to be read. > Is this in fact the case? Does this then mean that no greater speed is > possible for data exchange operations without moving to faster components? As a disclaimer, I'm not very familiar with DRAMS, but am familiar with psuedo-static RAMs. That said... A true PS RAM requires a clock to cycle between a "precharge" and an "access" phase. During precharge, all internal bitlines (the actuall connections to the output of the RAM cells) are charged to a static state, usually HIGH. The requires Tpre amount of time. During a read, the accessed call must then pull a charged bitline low to read a 0 state, but simply leaves the bitline in a charged state to read a 1 (or vice versa) rather then pulling it high. This takes Tacc time. The total cycle time, Tcyc = Tpre + Tacc. For a write, things are not (necessarily) the same. The way we spec our write time for PS RAMs is the amount of time that it takes to move a bitline to it's opposite state, and write the cell connected to that bitline. So the time to write a 1 is the time it takes to over-write a cell containing a 0, and vice versa to write a 0. The Twrite is the maximum of these two. Notice that the write does *NOT* take into account Tpre, nor is it required that a precharge occur before a write, because of the way we spec it (also note, however, that I do not know what convention is used by others). For simplicity sake, though, Tcyc is still spec'd as Tpre + Tacc, given that Twrite < Tacc, and the part is clocked. We have also started to spec a Trmw (read-modify-write time, what you asked about), which we define as Tpre + Tacc + Twrite, which is roughly 1.5*Tacc. Some SRAMs (static RAMs), and I assume some DRAMs as well, may be PS internally, generating the required clock on-chip, so that the user doesn't have to worry about it. This also may make it tough to determine what Trmw is, or it may require that Trmw = 2*Tcyc. Again, it depends on the part. Drop me a line of you have any more questions. -- Disclaimer: All spelling and/or grammar in this document are guaranteed to be correct; any exseptions is the is wurk uv intter-net deemuns,. Mike McManus Mike.McManus@FtCollins.NCR.COM, or NCR Microelectronics ncr-mpd!mikemc@ncr-sd.sandiego.ncr.com, or 2001 Danfield Ct. uunet!ncrlnk!ncr-mpd!garage!mikemc Ft. Collins, Colorado (303) 223-5100 Ext. 378