Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!apple!amdcad!mozart.amd.com!paul
From: paul@mozart.amd.com (Paul Schnizlein)
Newsgroups: comp.arch
Subject: Branch Target Caches (was: Smart I-cache?)
Summary: every non-sequential fetch is cached
Keywords: BTC, smart icache
Message-ID: <1990Dec3.202239.13188@mozart.amd.com>
Date: 3 Dec 90 20:22:39 GMT
References: <657720712@lear.cs.duke.edu> <MOSS.90Nov24181741@ibis.cs.umass.edu> <1990Nov26.205811.27083@zoo.toronto.edu>
Organization: Advanced Micro Devices, Inc.
Lines: 19

In article <1990Nov26.205811.27083@zoo.toronto.edu> henry@zoo.toronto.edu (Henry Spencer) writes:
>
>???  The AMD 29k BTC, the major example that I know about, works regardless
>of what kind of branch you use.  It even works on interrupts, as I recall.

Yes, it also caches targets of traps, and returns from interrupts and
traps.  That is, it caches the target instruction(s) of every
non-sequential fetch.

By the way, the Am29000 cache stored 4 instructions at the target of
each branch. The new Am29050 cache can be configured by the user to
store 4 or 2 instructions. Storing only 2 means more blocks 
are available in the fixed 1 kbyte storage space. This allows a
higher hit rate. With a memory system that can return a first access
in 2 wait cycles, this is especially attractive.

-- 
"It's never too late to have a happy childhood"
paul@mozart.amd.com (Paul Schnizlein) 


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