Path: utzoo!censor!geac!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!usc!apple!netcom!feustel
From: feustel@netcom.UUCP (David Feustel)
Newsgroups: comp.arch
Subject: Real 46 Bit Addressing in the 386/486!!!
Keywords: Intel 386 486
Message-ID: <17945@netcom.UUCP>
Date: 3 Dec 90 01:31:54 GMT
Organization: DAFCO - An OS/2 Oasis
Lines: 26


In a previous posting, citing the 386/486 inability to use full sized
32 bit segments, I suggested a hardware modification for the Intel
80586 chip which would permit the use of segments of length 2**32. I
have since discovered a method which permits the use of multiple 4
gigabyte data segments with the 386/486.

The method is to mark the descriptors of all full sized segments as not
present. Since the segment is not present, its address space is not
mapped into the 32 bit virtual address space. When a reference is made
to an address in one of these full sized segments, a segment fault occurs. The
kernel analyses the instruction and simulates the faulting instruction after
accessing a file containing the (sparse) segment data and either
reading from or writing to the file the operand specified by the faulting
instruction.  The kernel then updates the ip and other registers
involved and restarts the faulting task.

This method permits the use of almost all data segments except stack
segments as 32 bit segments; it is a *little* slower than the previously
suggested hardware modification but does vastly increase the available
address space. If you would rather have (faster) hardware support which
would also permit 2**32 bit code and stack segments, speak to Intel about it.

-- 
David Feustel, 1930 Curdes Ave, Fort Wayne, IN 46805, (219) 482-9631
EMAIL: netcom.uucp


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