Newsgroups: comp.arch Path: utzoo!utgpu!watserv1!watdragon!spurge!ccplumb From: ccplumb@spurge.uwaterloo.ca (Colin Plumb) Subject: Re: Branch Target Caches (was: Smart I-cache?) Message-ID: <1990Dec5.015650.5995@watdragon.waterloo.edu> Keywords: BTC, smart icache Sender: daemon@watdragon.waterloo.edu (Owner of Many System Processes) Organization: University of Waterloo References: <657720712@lear.cs.duke.edu> <1990Nov26.205811.27083@zoo.toronto.edu> <1990Dec3.202239.13188@mozart.amd.com> Date: Wed, 5 Dec 90 01:56:50 GMT Lines: 16 >In article <1990Nov26.205811.27083@zoo.toronto.edu> henry@zoo.toronto.edu (Henry Spencer) writes: >> >> ??? The AMD 29k BTC, the major example that I know about, works regardless >> of what kind of branch you use. It even works on interrupts, as I recall. In article <1990Dec3.202239.13188@mozart.amd.com> paul@mozart.amd.com (Paul Schnizlein) writes: > Yes, it also caches targets of traps, and returns from interrupts and > traps. That is, it caches the target instruction(s) of every > non-sequential fetch. It also caches page boundaries. I thought this was really nifty the first time I heard about it, until I realized the simple implementation: basically, when the processor negates the burst request line, it turns on the BTC. -- -Colin Brought to you by Super Global Mega Corp .com