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From: xaandrews@levels.sait.edu.au
Newsgroups: comp.dsp
Subject: Algorithms for phase locked loop?
Message-ID: <15731.275b9752@levels.sait.edu.au>
Date: 4 Dec 90 12:32:18 GMT
Organization: Sth Australian Inst of Technology
Lines: 10


        Has anyone got an algorithm for implementing a phase locked loop on a
digital signal processor?
 
        I am using a DSP-32C DSP chip from AT&T.
 
        Thanks in anticipation.
 
        David Hichens.
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