Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!pacific.mps.ohio-state.edu!linac!att!cbnewse!cwpjr
From: cwpjr@cbnewse.att.com (clyde.w.jr.phillips)
Newsgroups: comp.lang.forth
Subject: HARRIS RTX ? and Zilog ?
Keywords: Summary needed
Message-ID: <1990Dec5.170506.3438@cbnewse.att.com>
Date: 5 Dec 90 17:05:06 GMT
Distribution: na
Organization: AT&T Bell Laboratories
Lines: 25

Could someone get the complete story of the Harris RTX situation
( Phil K? ) and post the summary. Right now I expect that it's
still available but (marketing) de-emphasized, and won't become
*REAL* cheap soon 'cause of Die size. That's all I've heard
and I don't know if this is correct.

The complete summary would also include Harris's stance on
support, summary and status of the Design Contest, etc.

I'd also welcome any discussion of creating "generic"
FORTH engines using FPGA's that WOULD BE affordable
on singles quantities. I beleive we are at the gate count
with multi-funtional partitioning in these type "commodity"
parts to open this discussion.

I'll refrain from sheeding any tears till I know whether
it's warranted or not...

--Clyde
P.S. The Zilog thing is does anyone have FORTH's for the Super Z-8,
and did you hear Zilog upgraded the Z8 to have 16 bit math at < 2us
for divides and multiplies. Their market research showed they could
stem the tide toward 16bit parts with this move.
They say this 20mhz part will handle implemeting a SCSI adapter
now that it has 16bit math...


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