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From: ph@ama-1.ama.caltech.edu (Paul Hardy)
Newsgroups: comp.sys.mips
Subject: Re: MIPS assembler question
Message-ID: <PH.90Dec4113423@ama-1.ama.caltech.edu>
Date: 4 Dec 90 19:34:23 GMT
References: <PH.90Nov30111139@ama-1.ama.caltech.edu> <43786@mips.mips.COM>
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In-Reply-To: rowen@mips.COM's message of 4 Dec 90 18:10:36 GMT
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In article <43786@mips.mips.COM> rowen@mips.COM (Chris Rowen) writes:

   1) An ADD cannot start or finish in cycle in which a MUL starts or finishes
   2) Only one instruction can start in any cycle
   3) A load can finish in any cycle   

   This means that the add cannot start until the multiply has completed
   ...
   If you can reorder the code a little, it should get faster
   ...
[preferred order: mul.s, add.s, lwc1, mul.s, add.s, lwc1, etc.]

   Chris Rowen				

Someone else at MIPS, Mark Johnson, mentioned this to me yesterday.
The bottom line is that the floating-point adder, multiplier, and divider
circuits all share one exponent adder.  I had erroneously assumed that
they each had their own.  For operations using the floating-point adder,
multiplier or divider, this exponent adder is used during the first cycle
for exponent approximation, and the last cycle for normalization.

Therefore, these operations should be arranged so that they don't end
on the same cycle, and so that one does not begin on the same cycle
that another one ends.  A stall of the pending floating-point operation
will result.  This wasn't obvious from Kane's book.

Mark also pointed me to an excellent article (written by him, Chris,
and Paul Ries): "The MIPS R3010 Floating-Point Coprocessor" IEEE Micro,
June 1988, pp. 53-62.  I recommend this to anyone who wants to write
floating-point assembly code for the R3010; I have a much better
understanding of the chip after reading this article.

Thanks to both of you for your very helpful advice on this problem.

                              --Paul