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From: jws@thumper.mlb.semi.harris.com (James W. Swonger)
Newsgroups: sci.electronics
Subject: Re: schmitt trig. nand configurations
Message-ID: <1990Dec3.144646.619@mlb.semi.harris.com>
Date: 3 Dec 90 14:46:46 GMT
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 Paralleling inputs on 74{L,LS,S}13 gates does not increase the load current
appreciably. There is only one pullup resistor on the input, which any of the
diodes can pull down. The only loading penalty you pay is the pin capacitance
which is probably insignificant. (The spec is usually 5pF but a real package
is practically unmeasurable). The paralleled pins may in fact improve your
delay by a nanosecond. The other point to consider is that some families of
TTL do not respond well to having inputs tied to Vcc. LSTTL is OK, but I
recall having S-series parts getting hurt. The TI "bible" indicates that only
LS parts should be directly connected to Vcc; the other 4 (_, L, H, S) types
should have a limiting resistor.


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