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From: whit@milton.u.washington.edu (John Whitmore)
Newsgroups: sci.electronics
Subject: Re: Spice models of motherboards; PCB layout programs; DRAM controllers
Message-ID: <12356@milton.u.washington.edu>
Date: 5 Dec 90 06:57:09 GMT
References: <13970@june.cs.washington.edu>
Organization: University of Washington, Seattle
Lines: 38

In article <13970@june.cs.washington.edu> robertb@june.cs.washington.edu (Robert Bedichek) writes:
>I am designing a multiprocessor and I have some questions about how to
>design parts of it.
>
>The backplane and the boards that will plug into it are special for
>this machine, i.e., I'm not using VME, Futurebus, etc.  I need to know
>how fast I can run the bus and what kind of drivers, connectors, and
>termination that it will need.  Is modelling backplanes and bus
>transceivers with a circuit simulator viable?  Each bus in this system
>will have 8 boards on it, with between 16" and 40" of backplane trace
>per signal wire.  I'd like to clock it at 40ns.  Is this possible?
>Would I get a signal-quality benefit by using surface mounted drivers?

	There are SPICE hooks for all the varieties of behavior your
PC board might have, BUT it is very challenging to reduce the known
(mechanical) properties of the printed circuit to signal path electrical
parameters.  Various vendors have controlled-impedance wiring schemes
which can be tailored to your choice of buss driver/terminator.
One, in particular, Kollmorgen Corp., has a technique "Multiwire"
which is fast, well-characterized at high frequencies, and provides 
relatively quick turnaround on prototypes.  Instead of a printed circuit,
they route glue-coated insulated wires by mechanical placement.
Controlling capacitance is only part of the solution; you also need
to control inductance (trace width) and ensure the termination is
correct for the impedance of the traces.
	You might look at the National Semiconductor BTL bus drivers/
receivers.  These use non-TTL logic levels on the bus, with some
substantial gains in bus loading (the transmission line is
disturbed by each device connected to the bus, regardless of whether
it is active or tri-state) and drive capability (they will drive a
bus load of 18 ohms).  I can highly recommend the NS Interface Databook
and AN-458 (page 2-76) gives a very useful discussion of bus driving.
	The numbers favor you; 40 ns with 3' of distance is just
barely possible with printed circuitry, and relatively easy with
differentially driven twisted pair (typically used for fast ECL).

	John Whitmore
	Physics, U. of Wa.


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