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From: ken@csis.dit.csiro.au (Ken Yap)
Newsgroups: sci.electronics
Subject: Re: schmitt trig. nand configurations
Message-ID: <1990Dec5.013013.10298@csis.dit.csiro.au>
Date: 5 Dec 90 01:30:13 GMT
References: <48711@eerie.acsu.Buffalo.EDU> <153933.28651@timbuk.cray.com>
Organization: CSIRO Division of Information Technology
Lines: 26

>> i have a circuit which uses a 74xx13 schmitt triggered dual 4 input
>> nand in the following configurations;
>> 
>
>              Edited..
>
>>                                                       the top one has all
>> it's inputs tied to one which produces an inverted output.  the bottom one
>> is only dependant upon one of it's inputs since the other 3 are tied to Vcc.
>> thus since it is a nand gate it will have the same outcome as the
>> as the first circuit, (an inverter).
>> 	is there any special reason for configuring it in the two different
>> ways, i.e. faster responce, or sinking more current?
>> 				brian wybaillie
>
>    The logic producing the input for the first nand will have to drive 4 loads
>and the second one will only have to drive one load.

It depends on the guts of the NAND gate. If you look at the circuit
diagram of a typical N-input NAND gate there's only one resistor from
Vcc to the base of the multi-emitter transistor so paralleling the
inputs doesn't result in more current to sink. On the other hand, the
capacitive load will certainly increase, with more protective diodes to
ground so pulling up will be slowed. So yes, tie to Vcc if you can.

I don't know if the Schmitt NAND has only one base for all the inputs.


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