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From: msp33327@uxa.cso.uiuc.edu (Michael S. Pereckas)
Newsgroups: comp.arch
Subject: Re: RISCizing a CISC processor
Message-ID: <1990Dec7.061826.28241@ux1.cso.uiuc.edu>
Date: 7 Dec 90 06:18:26 GMT
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In <9012070105.AA02416@hcrlgw.crl.hitachi.co.jp> joe@hcrlgw.crl.hitachi.co.JP (Dwight Joe) writes:

>I would like some input on the following idea to extend the life of
>CISC processors.

>Consider a hypothetical machine: IM 68386C (CISCized).
>First, determine the dynamic instruction profile of the target mix.
>If the target is engineering programs, then determine the dynamic
>frequency of all instructions.  (A LOAD with indirect addressing
>and a LOAD with direct addressing are considered different instructions
>in the context of this posting.)

>Then, rank the instructions from highest frequency to lowest.
>Exclude I/O instructions.  Suppose that there are a total of "n" non-I/O
>instructions.  Suppose that I[n] is the instruction with the highest
>frequency and that I[1] is the instruction with the lowest frequency.

[deletion]

>In a CISC chip, there is a certain redundancy.  In other words,
>some of the complex instructions can be written in terms of the
>simpler instructions.  An instruction to move a block of data
>from one place in memory to another place can be replaced
>by a loop of simpler LOAD and STORE instructions.

[deletion]

>Now, using timing analysis, estimate the performance of
>implementing the RISC Set and the I/O Set in hardware
>and implementing the CISC Set as subroutines in
>a microcode store.  These subroutines are written with
>instructions from the RISC Set.  Whenever an instruction from
>the CISC Set is encountered in the instruction stream, it
>causes a trap to the appropriate subroutine in the
>microcode store.  Essentially, what we have is a
>RISC machine with some subroutines coded into ROM.

[deletion]



What about instruction decode?  RICS machines tend to have
fixed-format instructions that are easy to decode.  (i.e.  all
instructions are 32 bits, the first 6 are opcode, the next 15 specify
registers, the rest immediate data).  CISCs tend to have instructions
of varying length and format.  RISCs tend to have alignment
restrictions to a greater extent than CISCs.  You lose some of the
benefits of RISC if you have to deal with these things.
Does anyone know how the internals of the 80486 and 68040 compare to
this scheme?
--


Michael Pereckas               * InterNet: m-pereckas@uiuc.edu *
just another student...          (CI$: 72311,3246)
Jargon Dept.: Decoupled Architecture---sounds like the aftermath of a tornado