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From: hrubin@pop.stat.purdue.edu (Herman Rubin)
Newsgroups: comp.arch
Subject: Re: RISCizing a CISC processor
Summary: What about the instructions which did not show up in your sample?
Message-ID: <2454@mentor.cc.purdue.edu>
Date: 8 Dec 90 15:10:11 GMT
References: <9012070105.AA02416@hcrlgw.crl.hitachi.co.jp>
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In article <9012070105.AA02416@hcrlgw.crl.hitachi.co.jp>, joe@hcrlgw.crl.hitachi.co.JP (Dwight Joe) writes:
> I would like some input on the following idea to extend the life of
> CISC processors.

			.......................

>                  instruction       dynamic frequency
>                     I[1]                22%
>                     I[2]                8%
>                      .                  .
>                      .                  .
>                      .                  .
>                     I[n - 1]            0.002%
>                     I[n]                0.001%
> 
> In a CISC chip, there is a certain redundancy.  In other words,
> some of the complex instructions can be written in terms of the
> simpler instructions.  An instruction to move a block of data
> from one place in memory to another place can be replaced
> by a loop of simpler LOAD and STORE instructions.

What about the operations which did not appear in the sample?  Calculations
using high precidion arithmetic may not even be identified as such.  What
about conversion between integer and floating point?  On machines with
the possibility of unnormalized floating point, would they even be recognized?
On machines such as the IBM 360 series or the RS/6000, for which the
conversions are clumsy and already comples, would they be noticed?

Suppose that the CISC machine being analyzed has common integer and floating
registers.  Would the analysis catch the cases in which Boolean operations
are used on floats?  Suppose the machine has unaligned capabilities.  Would
the analysis catch those cases in which it was deliberately used in the
algorithm?

What we need is not the analysis of the current bad software for the needed
instructions, but to ask the few who can think up new ways of using the
natural capabilities of hardware what can be useful.  Even then, much will
be missed.

Also, what is a simple instruction?  Which is conceptually simpler, finding
the distance to the next one in a bit stream, with the attendant problems 
about running out of bits, etc., or the clumsy way this must be approached
on the so-called "efficient" architectures?
--
Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907-1399
Phone: (317)494-6054
hrubin@l.cc.purdue.edu (Internet, bitnet)   {purdue,pur-ee}!l.cc!hrubin(UUCP)