Path: utzoo!censor!geac!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!elroy.jpl.nasa.gov!ames!amdahl!JUTS!duts!kls30 From: kls30@duts.ccc.amdahl.com (Kent L Shephard) Newsgroups: comp.arch Subject: Re: RISCizing a CISC processor Message-ID: Date: 7 Dec 90 15:06:01 GMT References: <9012070105.AA02416@hcrlgw.crl.hitachi.co.jp> Sender: netnews@ccc.amdahl.com Reply-To: kls30@DUTS.ccc.amdahl.com (Kent L. Shephard) Distribution: na Organization: Amdahl Corporation, Sunnyvale CA Lines: 20 That sounds like the '040 and the i486. Both have RISC cores and use microcode for the more complicated instructions. Both companies saw that the only way to gain speed was to hardwire most of the processor, and put a decent pipeline in them. They also solve some memory problems with on chip cache. The i486 now does loads & stores in one clock cycle and if you don't worry about the pipline latency, the i486 running sequential code is very fast. Both processors have performance better than 1st generation RISC ie. the first SPARC from Sun. (The 460 was the first.) I've heard that the i586 will be out around '92' and will be super scalar. (But that just rumours.) Kent -- /* -The opinions expressed are my own, not my employers. */ /* For I can only express my own opinions. */ /* */ /* Kent L. Shephard : email - kls30@DUTS.ccc.amdahl.com */