Path: utzoo!censor!geac!torsqnt!news-server.csri.toronto.edu!cs.utexas.edu!know!news.cs.indiana.edu!msi.umn.edu!cs.umn.edu!mike From: mike@cs.umn.edu (Mike Haertel) Newsgroups: comp.arch Subject: Re: RISCizing a CISC processor Message-ID: <1990Dec7.193852.20921@cs.umn.edu> Date: 7 Dec 90 19:38:52 GMT References: <9012070105.AA02416@hcrlgw.crl.hitachi.co.jp> <1990Dec7.061826.28241@ux1.cso.uiuc.edu> <2339.275f7e44@iccgcc.decnet.ab.com> Organization: Free Software Foundation Lines: 10 Certainly RISCizing a CISC processor has been done, in the 68040 and 80486. The big problem I see with it is, why waste all that silicon space on the hair necessary to pipeline a complex instruction set? I think it would be far more worthwhile to waste it on things like faster multipliers or larger caches. -- Mike Haertel "There are two ways of constructing a software design. One way is to make it so simple that there are obviously no deficiencies, and the other is to make it so complicated that there are no obvious deficiencies." -- C. A. R. Hoare