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From: mef@aplcen.apl.jhu.edu (Marty Fraeman)
Newsgroups: comp.lang.forth
Subject: Re: FPGA Forth engines
Summary: You could do it but it wouldn't be too great
Message-ID: <1990Dec7.143245.29515@aplcen.apl.jhu.edu>
Date: 7 Dec 90 14:32:45 GMT
References: <9012061501.AA20109@ucbvax.Berkeley.EDU> <1990Dec6.223103.5766@cbnewse.att.com>
Reply-To: mef@aplcen (Marty Fraeman)
Distribution: na
Organization: Johns Hopkins University
Lines: 50

Well, as a fellow who's actually built 3 forth chips I just couldn't
keep my trap shut any longer on the economics of building processors
and using FPGAs as an implementation technology.

Certainly Mitch's comments regarding the economics of processor are
design are valid.  So to do a new Forth chip based solely on the hope
that you'd make money selling the chips themselves seems pretty
unlikely to me.  But other factors should also be considered.  For
example, the argument I've been able to use around here is that we can
build and program a one a kind embedded system far less expensively
based on a Forth chip than with traditional ways.  The language itself
accounts for some of this naturally, but the chip is needed to give us
acceptable performance at the same time.  In fact this tradeoff is so
dramatic that the processor development effort (especially with the
productivity possible with modern silicon design tools) can pay for
itself on the first project that uses it!

Now onto FPGA built processors.  There is absolutely no doubt in my
mind that you could build a processor of some sort using FPGAs.  I
suspect you could even do something like my favorite machine (the SC32
of course -) although other approachs might better suit the building
blocks in a FPGA (i.e. I suspect Phil's WISC architecture would work
out pretty well).  Ah, but how fast would such a machine be?  Sloooooow
(Well, in my opinion anyway.  I suppose someone'll build it and make me
a liar but until then ...).  The programmable wire routing between
logic elements adds lots of capacitance so lots of electrons need to
wander back and forth and that all takes time.  For example, how come
the RTX2000, a 16 bit standard cell design, and the SC32, a 32 bit
compiled chip, both run at 10 MHz?  The SC32 is a 2u part and I think
the RTX is too.  The data path of the SC32 is essentially a custom
design so wire paths are short and loading is minimal.  The RTX data
path is logic gates lined up in neat rows with lots of computer placed
wire hooking up the gates to do things.  That slows stuff up (a lot in
the case of the data path).  Yet the RTX standard cells are dense and
close together compared to an FPGA.  So I think you'd be lucky to get
1-5MHz out of an FPGA based processor.  At those speeds the fancy new
chips (SPARC, MIPS, AMD29000, M88000, ...) could probably run Forth
almost as fast as your machine while they'd be cheaper, lower power,
less board space, etc.



	Marty Fraeman

	mef@glinda.jhuapl.edu
	301-953-5000, x8360

	Room 13-s587
	Johns Hopkins University/Applied Physics Laboratory
	Johns Hopkins Road
	Laurel, Md. 20723