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From: peterl@ibmpcug.co.uk (Peter Leaback)
Newsgroups: eunet.micro.acorn,comp.sys.acorn,connect.audit
Subject: Re: Aligning assembly language programs.
Message-ID: <1990Dec7.012835.3319@ibmpcug.co.uk>
Date: 7 Dec 90 01:28:35 GMT
Organization: The IBM PC User Group, UK.
Lines: 23


Because of the way memory works, each time the processor fetches an
instruction which crosses a Quad Word boundary an extra cycle is used. 
So if 4 words are fetched then an extra cycle can be saved if it is Q.W.
aligned, but if 5 words are fetched then it may not make the difference.
Anyway the effect is slight and not as much as 5% on a good chunk of
code.

Talking about an ARM3, it makes more of a difference because the cache
fetches Q.W. aligned data, so it may fetch data that isn't needed.


>idea - although I haven't studied the PRMs or Intel's ARM chip set data

Intel !! wash your mouth out.

Peter Leaback.

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