Path: utzoo!utgpu!cunews!cognos!alzabo!andras
From: andras@alzabo.uucp (Andras Kovacs)
Newsgroups: eunet.micro.acorn,comp.sys.acorn,connect.audit
Subject: Re: Aligning assembly language programs.
Message-ID: <1990Dec8.083336.7855@alzabo.uucp>
Date: 8 Dec 90 08:33:36 GMT
References: <1990Dec7.012835.3319@ibmpcug.co.uk>
Reply-To: andras@alzabo.UUCP (Andras Kovacs)
Organization: Brian's XENIXlings, Ottawa, Canada
Lines: 20

In article <1990Dec7.012835.3319@ibmpcug.co.uk> peterl@ibmpcug.co.uk (Peter Leaback) writes:
>
>Because of the way memory works, each time the processor fetches an
>instruction which crosses a Quad Word boundary an extra cycle is used. 
>So if 4 words are fetched then an extra cycle can be saved if it is Q.W.
>aligned, but if 5 words are fetched then it may not make the difference.
>Anyway the effect is slight and not as much as 5% on a good chunk of
>code.
>
    I wouldn't say 'because of the way memory works'. This characteristics
of the Archimedeses exists because the memory controller able to exploit the
fast page mode access capabilities of modern DRAM's:
    "MEMC uses the page mode access capability of DRAMs, where, once a row
address has been strobed into the DRAM, any column in that row may be accessed
merely by strobing in the new column address." (VL86C010 32-bit RISC MPU and
Peripherals Users Manual, VLSI Technology, Inc., 1989).
    5% can make a big difference deep inside a nested loop!
-- 
Andras Kovacs
andras@alzabo.UUCP