Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!cbmvax!raible
From: raible@cbmvax.commodore.com (Bob Raible - LSI Design)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: NEC 2A question
Message-ID: <16390@cbmvax.commodore.com>
Date: 9 Dec 90 21:20:21 GMT
References: <1990Dec5.155357.3957@intelhf.hf.intel.com> <16335@cbmvax.commodore.com> <1990Dec7.154431.1952@intelhf.hf.intel.com>
Reply-To: raible@cbmvax.commodore.com (Bob Raible - LSI Design)
Organization: Commodore, West Chester, PA
Lines: 52

In article <1990Dec7.154431.1952@intelhf.hf.intel.com> griff@anvil (Richard Griffith) writes:
>In article <16335@cbmvax.commodore.com> raible@cbmvax.commodore.com (Bob Raible - LSI Design) writes:
>>In article <1990Dec5.155357.3957@intelhf.hf.intel.com> griff@anvil.intel.com (Richard Griffith) writes:
>>>How difficult is it to hook up a NEC Multisync 2A to a 2000?
>>>anyone know? (awww, comeon, someone here knows... :-)                   
>>>               
>>>                       - griff
>>>
>>>:Richard E. Griffith, "griff" : iNTEL, Hillsboro Ore.
>>>:griff@anvil.hf.intel.com
>>>:SCA!: Cyrus Hammerhand, Household of the Golden Wolf, Dragons' Mist, An Tir 
>>>:These are MY opinions, if iNTEL wanted them, They'd pay for `em!
>>
>>I currently use this combination at work. As you note I am a chip
>>designer and not  an official spokesman for this type of thing, so I am
>>not certain as to what the "official" advice is. What I have noted is
>>that if productivity mode operation is desired(when 2.0 is available to
>>2000 owners) then it is necessary to use separate syncs and not the
>>CSYNC signal. However during boot phase HSYNC and VSYNC outputs are
>>momentarily tri-stated and checked for the presence of an external
>>source of syncs(genlock). However presence of 75ohm pulldowns on NEC2A
>>sync inputs, the levels are less than ideal and the software wrongly
>>concludes that an external device is trying to supply syncs and will
>>provide synchronized 28MHz as well. Consequently the internal 28MHz
>>clock is disconnected and the system hangs.
>>
>>The upshot of the above discussion is that ideally the hsync and vsync
>>signals will be buffered before being connected to monitors having 75ohm
>>terminations. Typically a TTL buffer is wired into the hood of the
>>B2000 video connector. The other alternative is to use CSYNC instead,
>>but as mentioned above, CSYNC won't be available when using any of the
>>new ECS programmable modes(640x400,1280x200 noninterlaced).
>>
>>Hope this helps - sure beats trying to figure out why your new monitor
>>keeps causing your 2000 to hang!
>
>hanging? are we talking about the same article?  I haven't yet
>hooked the 2a up yet (does the above tell me that this is a little 
>tricky?) 
>
>                                       - griff
>
>
>-- 
>:Richard E. Griffith, "griff" : iNTEL, Hillsboro Ore.
>:griff@anvil.hf.intel.com
>:SCA!: Cyrus Hammerhand, Household of the Golden Wolf, Dragons' Mist, An Tir 
>:These are MY opinions, if iNTEL wanted them, They'd pay for `em!

As I mentioned the system WILL hang . This is a prediction of a future
occurence, not a re-hash of the past. To repeat,the proper cable would
buffer horizontal and vertical syncs.