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From: andrew@frip.WV.TEK.COM (Andrew Klossner)
Newsgroups: comp.sys.m88k
Subject: Re: m88200 cache flushes on DG Aviion
Message-ID: <9675@orca.wv.tek.com>
Date: 7 Dec 90 21:25:50 GMT
References: <2308@io.UUCP>
Sender: nobody@orca.wv.tek.com
Reply-To: andrew@frip.wv.tek.com
Organization: Tektronix, Wilsonville, Oregon
Lines: 23

[]

	"I would like to request a specific line flush from the m88200
	cache handling instructions.  I'm not too keen on a full flush
	of both caches, as that would take too much time."

In the Motorola kernel, the time it takes to flush the cache is small
compared to the time it takes to get into and out of the system call
handler.  I'd be surprised if Data General has significantly smaller
syscall overhead.

	"The code is apparently failing because the contents of the two
	caches different values for the same address.  Why wasn't this
	state prevented by the "M-bus snooping" of the 88200's?"

Again, in the Motorola kernel, only the data caches are told to
participate in snooping.  Performance would be seriously degraded if
the instruction caches were to join in.  On a snoop cycle, *every*
snooping 88200 must stop what it's doing for one cycle and listen in.
Even if the CPU is fetching instructions from cache, it's held up.

  -=- Andrew Klossner   (uunet!tektronix!frip.WV.TEK!andrew)    [UUCP]
                        (andrew%frip.wv.tek.com@relay.cs.net)   [ARPA]