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From: lrm3@ellis.uchicago.edu (Lawrence Reed Miller)
Newsgroups: comp.sys.mac.misc
Subject: Re: The New Macs: Greedy Compromises?
Message-ID: <1990Dec7.065300.6932@midway.uchicago.edu>
Date: 7 Dec 90 06:53:00 GMT
References: <1142@duteca.UUCP> <1990Dec2.084149.25494@world.std.com> <130024@jake.encore.com>
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wcarroll@encore.com (Mr. New Dad) writes:
>>
>> What do you mean by 'incompatible architecture'? The 68020 instruction
>> set is actually a SUPERSET of the 68030!
>>
>
>Back to the 68030 User's Manual, the '020 has two instructions (CALLM
>and RTM) not in the '030, and the '030 has four MMU instructions (PFLUSH,
>PLOAD, PMOVE, and PTEST) not in the '020. The only other differences
>listed are: 128 byte data cache, on-chip MMU, and 6 new control registers.

While it is true that the 68020 chip itself does not have these memory  
management instructions, they can be added if a 68851 MMU is added to the
68020 system.  Adding a 68851 will give you a superset of the 68030 MMU
instructions (for instance, PBcc, which is not supported by the '030).  So if
you need these intructions (for virtual memory support) you _can_ get them
on a 68020 system.  Of course, programs written (properly) for the macintosh
would never call any of these instructions, anyway, as they are privileged
and therefore forbidden (by Apple) to be used by applications, etc.  So the
lack of these instructions shouldn't ever cause any problems on a non 68851
'020 system.  "Thou Shalt not Assume that Thy Macintosh is in Supervisor Mode"

Also, the caches on the 68030 (both data and instruction)
are 256 byte, not 128 byte.  Not that this will ever affect code executing
on the processor, anyway...

Sources: Documents BR508/D Rev 2 (68030) and BR243/D Rev 3 (68020) (Motorola)

Just picking nits :^)  I generally agree with what you are saying...

Lawrence Miller