Path: utzoo!attcan!uunet!olivea!orc!inews!mipos2!dlau
From: dlau@mipos2.intel.com (Dan Lau)
Newsgroups: comp.arch
Subject: Re: RISCizing a CISC processor
Message-ID: <1311@inews.intel.com>
Date: 10 Dec 90 20:22:12 GMT
References: <9012070105.AA02416@hcrlgw.crl.hitachi.co.jp> <1200@dg.dg.com>
Sender: news@inews.intel.com
Reply-To: dlau@mipos2.UUCP (Dan Lau)
Organization: Microprocessor Component Group, Intel Corp., Santa Clara, CA
Lines: 19

In article <1200@dg.dg.com> uunet!dg!lewine writes:
>In article <9012070105.AA02416@hcrlgw.crl.hitachi.co.jp>, joe@hcrlgw.crl.hitachi.co.JP (Dwight Joe) writes:
>	***HOWEVER***, the advantage of RISC is moving work from 
>    runtime to compile time.  The big speedup comes from compiler
>    work not hardware. At Data General we have modified some of
>    the compilers for our CISC MV-series to compile simple code
>    instead of using instructions like WEDIT.  This has produced
>    major performance enhancements because a compiler can generate
>    special case code. 

I don't understand the comment above about the MV-series compilers.
Are you saying that after DG changed the MV-series compilers to generate
simple code, there was a major performance improvement (over the complex
code)?  Or are you saying that "because a compiler can generate special
case code" (i.e., very complex instructions like WEDIT), there was a
major performance enhancement over the simple code?

I am confused, can you please clarify the above.  Thanks.
	Dan Lau