Path: utzoo!utgpu!cunews!bnrgate!bwdls61.bnr.ca!bwdls58!mlord
From: mlord@bwdls58.bnr.ca (Mark Lord)
Newsgroups: comp.arch
Subject: Re: multiarchitecture chips (was Re: The CPU with 3 brains)
Message-ID: <5099@bwdls58.UUCP>
Date: 11 Dec 90 18:53:30 GMT
References: <1990Dec10.230226.13217@unixg.ubc.ca>
Sender: mlord@bwdls58.UUCP
Reply-To: mlord@bwdls58.bnr.ca (Mark Lord)
Distribution: na
Organization: Bell-Northern Research, Ottawa, Canada
Lines: 23

In article <1990Dec10.230226.13217@unixg.ubc.ca> thornburg@mtsg.ubc.ca (Jonathan Thornburg) writes:
< 
<I could go on, but I think the point is clear:  Dividing 1 million
<transistors into 7 140K-transistor CPUs will yeild 7 CPUs, each slower
<than a 1M-transistor CPU.

Quite possibly true, but speed is not the only design goal.
If it were, then we would only build Fugitsu [sic] supercomputers
(or maybe Crays), rather than wasting our time on 80486's and R3000's,
etc..

The idea with the multiple brains is that beyond a quickly approaching point,
it is difficult to provide increased  performance without investing much more
effort in to the rest of the design (off-chip).  So for THOSE applications,
what can one do with the extra half million transistors?  Aha.. why not make
the cpu more veratile:  with multiple brains, it is still of reasonable speed,
and can still be easy to interface/design around, AND we might be able to gain
a LARGE base of already-compatible software designed for other cpus.
-- 
 ___Mark S. Lord__________________________________________
| ..uunet!bnrgate!mlord%bmerh724 | Climb Free Or Die (NH) |
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