Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!udel!rochester!pt.cs.cmu.edu!gandalf.cs.cmu.edu!lindsay From: lindsay@gandalf.cs.cmu.edu (Donald Lindsay) Newsgroups: comp.arch Subject: Re: IO buses Message-ID: <11393@pt.cs.cmu.edu> Date: 14 Dec 90 00:08:30 GMT References: <11357@pt.cs.cmu.edu> Organization: Carnegie Mellon Computer Science or maybe Robotics Institute Lines: 32 In article pcg@cs.aber.ac.uk (Piercarlo Grandi) writes: >> I seem to recall a typical loaded Unibus getting rather under 1 MB/s. >The >Unibus was not the bottleneck; it could sustain memory-to-memory copies, >i.e. 3-4 MB/sec. on something like an 11/45, fairly well. I believe I was wrong: I should have said 1 MW/s, which is 2 MB/s. A device 'way out the end of a long daisy chain could spend around a microsecond on that "400 ns" cycle. This can be squared with your 3-4 MB/s by noting that the 11/45 had a fast CPU-memory path as well as its Unibus. >There are even drives, magnetic or not, whose mean undetected error rate >is of the same order as their capacity, so virtually guaranteeing that >you get an undetected error every time you make a copy of them. After >all even a fairly respectable undetected error rate of 1 in 10^12 is >usually expressed in bits. Good point! Creo's 1 TB optical tape holds 10^12 bytes and has "fewer than 1 in 10^12" bit errors. The pessimistic reading is as "fewer than 8 mistakes per reel". It doesn't wash to say that one is storing (say) images, where errors will be unnoticable. Images are usually stored in some compressed form, and decompression should be a pretty good error magnifier. Rather than expecting perfection, we should probably expect systems to have selectable, adjustable amounts of protection. -- Don D.C.Lindsay .. temporarily at Carnegie Mellon