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From: hoelzle@Neon.Stanford.EDU (Urs Hoelzle)
Newsgroups: comp.arch
Subject: Why do RISCs use (*not* need) fewer transistors?
Message-ID: <1990Dec14.001129.988@Neon.Stanford.EDU>
Date: 14 Dec 90 00:11:29 GMT
Organization: Computer Science Department, Stanford University
Lines: 21

The integer part of a typical RISC can be implemented with about 100K
transistors.  Current impementation technology allows >1M
transistors/chip (e.g. i486, 68040).  Why don't current RISC
implementations take advantage of the extra transistors and put a
large cache on the chip?  And/or an FPU?  For example (as far as I
know), typical SPARC chips neither have an on-chip FPU nor a large
cache; same for MIPS. 

One reason for a lower transistor count might be cost - but having
separate FPU or MMU chips doesn't exactly reduce system cost.  Or does
the better yield of the small chips outweigh the extra cost of having
several chips instead of just one?
Another reason would be faster implementation technology which doesn't
allow the same transistor density - but most popular RISC chips don't
run on a faster clock than, say, a 486.

So: why do RISC implementations currently use fewer transistors??
-- 
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Urs Hoelzle, CS PhD student			       hoelzle@cs.stanford.EDU
Center for Integrated Systems, CIS 42, Stanford University, Stanford, CA 94305