Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!usc!csun!nic.csu.net!csus.edu!ucdavis!csusac!croft
From: croft@csusac.csus.edu (Steve Croft)
Newsgroups: comp.arch
Subject: Re: Why do RISCs use (*not* need) fewer transistors?
Message-ID: <1990Dec14.153404.12210@csusac.csus.edu>
Date: 14 Dec 90 15:34:04 GMT
References: <1990Dec14.001129.988@Neon.Stanford.EDU>
Reply-To: croft@csusac.UUCP (Steve Croft)
Organization: California State University, Sacramento
Lines: 5

Panasonic has put their whole SPARC implementation (FPU, CPU, cache, etc)
on on chip.  And just lookit that heat sink!

Steve
stevec@water.ca.gov