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From: brandis@inf.ethz.ch (Marc Brandis)
Newsgroups: comp.arch
Subject: Re: Why do RISCs use (*not* need) fewer transistors?
Message-ID: <18164@neptune.inf.ethz.ch>
Date: 14 Dec 90 14:39:08 GMT
References: <1990Dec14.001129.988@Neon.Stanford.EDU>
Sender: news@neptune.inf.ethz.ch
Reply-To: brandis@inf.ethz.ch (Marc Brandis)
Organization: Departement Informatik, ETH, Zurich
Lines: 31

In article <1990Dec14.001129.988@Neon.Stanford.EDU> hoelzle@Neon.Stanford.EDU (Urs Hoelzle) writes:
>The integer part of a typical RISC can be implemented with about 100K
>transistors.  Current impementation technology allows >1M
>transistors/chip (e.g. i486, 68040).  Why don't current RISC
>implementations take advantage of the extra transistors and put a
>large cache on the chip?  And/or an FPU?  For example (as far as I
>know), typical SPARC chips neither have an on-chip FPU nor a large
>cache; same for MIPS. 

This is only true for what you find in current machines, but it is not true
for chips. E.g. the new MIPS R3300 (or maybe R3400, I do not exactly remember
the number) contains the FPU and caches on chip. There are SPARC 
implementations that have cache on chip. There are RISC CPUs like the i860
or the IBM RS/6000 that have around 1 million transistors on a chip (actually,
the RS/6000 uses 9 chips with almost 8 million transistors as a whole).

>One reason for a lower transistor count might be cost - but having
>separate FPU or MMU chips doesn't exactly reduce system cost.  Or does
>the better yield of the small chips outweigh the extra cost of having
>several chips instead of just one?

One or two years ago it may have been that the better yield would result in
lower cost as a whole. But the picture is changing. I think in one or two
years you will find a lot RISC workstations containing CPUs with 1 million
transistors.


Marc-Michael Brandis
Computer Systems Laboratory, ETH-Zentrum (Swiss Federal Institute of Technology)
CH-8092 Zurich, Switzerland
email: brandis@inf.ethz.ch