Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!att!tut.cis.ohio-state.edu!pt.cs.cmu.edu!spice.cs.cmu.edu!af From: af@spice.cs.cmu.edu (Alessandro Forin) Newsgroups: comp.arch Subject: Re: [m88200] cache flushes [on DG Aviion] Summary: Caches can be better, for RISC too Message-ID: <11421@pt.cs.cmu.edu> Date: 16 Dec 90 17:44:08 GMT References: <1990Dec15.143354.8493@ux1.cso.uiuc.edu> Organization: Carnegie-Mellon University, CS/RI Lines: 15 I was told on the IBM 6000 box there are instructions to flush (ranges of?) the cache at the user level. Seems to me this shows there is no inherent compelling architectural reason why RISC architectures should not provide a good cache interface to their users (both OS and applications) if they create the need for one. A system call is not a "good" cache interface. No matter how many standard commitee members you put on top of it. sandro- ----------------------------------------------------------------------------- Alessandro Forin / School of Computer Science / Carnegie-Mellon University Schenley Park / Pittsburgh, PA 15213 / Ph: (412) 268-6861 / FAX 681-5739 ARPA: af@cs.cmu.edu