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From: kapoor@wuee1.wustl.edu (Sanjay Kapoor)
Newsgroups: comp.dcom.lans
Subject: FDDI chip set (SUPERNET) query ....
Message-ID: <1990Dec14.222742.8116@cec1.wustl.edu>
Date: 14 Dec 90 22:27:42 GMT
Sender: news@cec1.wustl.edu (USENET News System)
Organization: Washington University, St. Louis MO
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I have a couple a questions related to the SUPERNET chip set. 

Q) Given that SUPERNET does not impose a restriction on the response time of
the interrupt latencies, what are the response times generally preffered?
Of course it does depend on the interrupt priorities, worst case traffic 
patterns of frame arrival etc. Some real numbers is what I am looking for.

Also in terms of performance, is it a good idea to run higher layer protocols
and do SUPERNET housekeeping within the same chip? Higher layer protocols like
say TCP/IP etc?
This is because besides DPC, and Node processor, the third DMA channel that 
RBC services is a chip that processes only the data frames. All control 
frames are routed to the node processor.

Suggestions/advice/Solutions are all greatly welcome.

Thanks

-Sanjay Kapoor
kapoor@wuee1.wustl.edu