Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!apple!vsi1!wyse!adyer From: adyer@milo.wyse.com (Andrew Dyer x2446) Newsgroups: comp.lang.forth Subject: Re: FPGA Forth engines Message-ID: Date: 11 Dec 90 02:06:23 GMT References: <9012061501.AA20109@ucbvax.Berkeley.EDU> <1990Dec6.223103.5766@cbnewse.att.com> <1990Dec7.143245.29515@aplcen.apl.jhu.edu> Sender: news@wyse.wyse.com Distribution: na Organization: Wyse Technology, Inc. Lines: 24 In-reply-to: mef@aplcen.apl.jhu.edu's message of 7 Dec 90 14:32:45 GMT I don't think your comments are necessarily true. Several vendors have arrays with approx. 2000 2-input NAND-equivalent gates, which will run at toggle rates of 70 MHz.(Xilinx and AMD) I wouldn't trust I/O rates to be more than 50 Mhz tho. Assuming a 50 MHz clock, and 6 clock cycles/instruction you get 8.33 MHz cycle rate. Not too shabby. The other problem is that FPGAs are expensive, and it would take several of them if they were the only components. For a one shot system that's o.k., but if it's to be ``public domain'' hardware, then it should be a bit simpler (IMHO). Rather than FPGA's exclusively, I would be inclined to use a mixture of LSI type parts like register files, dual port memories, ALU's and some FPGA logic for ``glue''. If one chose the correct parts, the design could be easily migrated to a standard cell or gate array library. (2900 series bit slice components, for example, are available from at least one vendor.) -- -- {uunet, mips, decwrl}!wyse!adyer or adyer@wyse.com "One day I asked the angels for inspiration, and the devil bought me a drink. He's been buying them ever since. "