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From: savel@hoss.unl.edu (Bharat P. Savel)
Newsgroups: comp.lsi.cad
Subject: help reqd. in VHDL (IEEE)
Message-ID: <1990Dec14.183623.26788@hoss.unl.edu>
Date: 14 Dec 90 18:36:23 GMT
Sender: news@hoss.unl.edu (Network News Administer)
Organization: Computing Resource Center, University of Nebraska
Lines: 62


i am having problems in the binding; i can't seem to bind generic maps; 
entity goes this way
entity name is
  generic (
      a : some_type
          );
  port (
      b : some_other_type;
      c : yet_another-type;
       );
end name;
---
architecture XX of name is
    ^
    |
    |
    |      
    v
end XX;
--- 
entity bench_name is
end bench_name;
---
architecture XX of bench_name is
  component name 
     generic(
       a : some_type;
            );
     port(
        b :  //
        c :  //
            );
   end component;
for all : name use work.entity name (XX)
     generic map(
        a => open
                );
     port map (
        b => b;
        c => c
              );
begin
     ^
     |
     |
     v
end;
-----------------------------------------------
for some reason i cannot have this kind of binding for generic maps; in
the past i have never used mapping for generics; the port maps work fine 
this way; any idea what am i dong wrong?

thanks 


    
--
--------------------------------------------------------------------------------
Bharat P. Savel
EE Dept.                                       e-mail : savel@engde001.unl.edu
Univ of Nebraska-Lincoln                           Ph : (402) 477-9857