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From: savel@hoss.unl.edu (Bharat P. Savel)
Newsgroups: comp.lsi.cad
Subject: Re : need help in VHDL (IEEE)
Message-ID: <1990Dec14.224133.28150@hoss.unl.edu>
Date: 14 Dec 90 22:41:33 GMT
Sender: news@hoss.unl.edu (Network News Administer)
Organization: Computing Resource Center, University of Nebraska
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me again;
some of you have mentioned that i should not have a semi-colon after the
generic statement end; true; i missed that; what i got was a SEM error; no
SYN; seems that the 'open' statement was giving me problems; tried every
possibility; declared them 'open' when defining the component, even
declared them 'open' during component instantization (positional binding);
prior to this i got an error at the component insantiation, saying that
wrong type/mode at the 'open' areas; i was under the impression that by declaring this 'open' during declaration of the component i needn't worry about it 
during instantiation; turned out wrong;
	the error i can't just get rid of is, "not all local ports are
connected to some formal port"; not true .... unless i am missing
something in the release notes; however , when i just remove all the ports
that i do not need, it works just dandy; get the right results; is it
possible that when working with 'open' generics, CONFIGURATION is a must?


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Bharat P. Savel
EE Dept.                                       E-mail : savel@hoss.unl.edu
Univ of Nebraska-Lincoln                           Ph : (402) 477-9857