Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!bbn.com!prost.bbn.com
From: tdonahue@prost.bbn.com (Tim Donahue)
Newsgroups: comp.realtime
Subject: Re: Realtime RISC?
Message-ID: <61499@bbn.BBN.COM>
Date: 11 Dec 90 14:57:36 GMT
References: <1990Dec4.193740.4430@nbc1.ge.com> <879@hrshcx.csd.harris.com>
Sender: news@bbn.com
Reply-To: tdonahue@prost.bbn.com (Tim Donahue)
Organization: BBN Advanced Computers, Inc.
Lines: 22
In-reply-to: steved@hrshcx.csd.harris.com (Steve Daukas)

In article <879@hrshcx.csd.harris.com>, steved@hrshcx (Steve Daukas) writes:
>
>Harris has a Real-Time Unix Kernal that runs on a M88100 RISC processor.
>This was designed for "Hard Real-Time" environments, those needing
>interrupt response times of less than 5 microseconds and context switch
>times of less than 50 microseconds.  The Kernal is SVID and SVVS and POSIX.
>
>Steve

Sounds like a nice product.  However, I was scratching my head about
that quoted interrupt response time.  This being an 88100, could you
please explain what you mean by "interrupt response time"?  Is this the
time from INT pin active to first instruction of user handler?  Have the
pipelines been drained?  Has shadowing been enabled?  Has the source of
the interrupt (I presume there is more than one) been established?
Could you please give the clock rate of the part?

I'd also be interested in knowing the context switch time with the
CMMUs disabled, if any are present.

Thanks very much,
Tim