Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!cs.utexas.edu!wuarchive!udel!haven!umbc3!gmuvax2!smasters From: smasters@gmuvax2.gmu.edu (Shawn Masters) Newsgroups: comp.sys.ibm.pc.hardware Subject: Re: EISA vs. ISA Message-ID: <3113@gmuvax2.gmu.edu> Date: 15 Dec 90 14:52:09 GMT References: <51097@eerie.acsu.Buffalo.EDU> <2638@sixhub.UUCP> Reply-To: smasters@gmuvax2.UUCP (Shawn Masters) Distribution: usa Organization: George Mason Univ. Fairfax, Va. Lines: 17 The original design of ISA, as defined by IBM, allows bus mastering. This is done by requesting the DMA, and then holding a MASTER line, until mastership is acknowledged. The card then had FULL access to all signals on the card edge(note: lines like IRQ0 and others are still CPU only lines, which means the interrupts serviced are only those of I/O devices). The limitations, all motherboard activity is stopped, including memory refresh. This means don't be a master for more then a couple microseconds or you lose trust in memory contents(although I've extenend my refresh on a 16MHz 286 upto 3 times a second with only a infrequent error. Note though that I was using REALLY fast chips, which may allow for less leakage. Not being a solid state specialist I don't know what realtionship is). Shawn Masters CNS George Mason University smasters@gmuvax2.gmu.edu